F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP

The following chapters describe implementation of the Intel® Agilex™ F-tile physical (PHY) layer IP, PLLs, and clock networks. Refer to these chapters for implementation details of IP instantiation, connection, simulation, and tile placement for Intel® Agilex™ F-tile designs.

Implementation of F-tile PMA/FEC PHY designs involves instantiation and connection of the following required and optional Intel® FPGA IP that is available in the Intel® Quartus® Prime IP catalog:

  • F-Tile PMA/FEC Direct PHY Intel® FPGA IP (Required)
  • F-Tile Reference and System PLL Clocks Intel® FPGA IP (Required)
  • F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP (Optional)17
This user guide organizes information into the following chapters describing the IP and implementation:
17 This IP is required only for dynamic reconfiguration, or controlling multiple IP with one user interface for reconfiguration. The IP accesses the global Avalon® memory-mapped hard register in F-tile for PMA setting reconfiguration.

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