F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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4.1. IP Parameters

Table 88.   F-Tile Reference and System PLL Clocks Intel® FPGA IP Parameters
Parameter Values Description
System PLL #0
Mode of system PLL 0, 1, 2 Selects the mode of system PLL #0.
  • Disabled— system PLL not used. You must enable at least one system PLL.
  • ETHERNET_FREQ_ <output-freq>_<refclk-freq>—presets for Ethernet use cases. output_freq is the system PLL output frequency and refclk_freq is the system PLL reference clock frequency.
  • PCIE_FREQ_<output-freq>— presets for PCIe use cases. output_freq is the system PLL output frequency.
  • User configuration—manually configures output frequency of system PLL and selects one of the feasible reference clocks. For use in non PCIe use cases when other Ethernet presets do not meet requirement.
  • User PCIe-based configuration— manually configures output frequency of system PLL and selects one of the feasible reference clocks. For use in PCIe use cases when PCIe presets do not meet requirement.
The frequency number in the preset’s label are abbreviated; they are not full precise frequency. Refer to the table below for full frequency. The default value is ETHERNET_FREQ_805_156.
User configuration
User PCIe-based configuration
ETHERNET_FREQ_805_156
ETHERNET_FREQ_805_312
ETHERNET_FREQ_805_322 37.
ETHERNET_FREQ_830_156
ETHERNET_FREQ_830_312
PCIE_FREQ_1000
PCIE_FREQ_500
PCIE_FREQ_550
PCIE_FREQ_600
PCIE_FREQ_650
PCIE_FREQ_700
PCIE_FREQ_750
PCIE_FREQ_800
PCIE_FREQ_850
PCIE_FREQ_900
PCIE_FREQ_950
Reference clock source Reference clock #0 Selects the logical reference clock source for system PLL #0. The reference clock source can be shared with FGT PMA and other system PLLs. The default value is Reference clock #0.
Reference clock #1
Reference clock #2
Reference clock #3
Reference clock #4
Reference clock #5
Reference clock #6
Reference clock #7
Reference clock #8
Reference clock #9
Output frequency 31.25 to 1000 MHz Specifies the output frequency of the system PLL #0 in MHz. In background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, specify the exact frequency with decimal points. The default value is 805.6640625.
System PLL #1
Mode of system PLL 0, 1, 2 Selects the mode of system PLL #1.
  • Disabled— system PLL not used. You must enable at least one system PLL.
  • ETHERNET_FREQ_ <output-freq>_<refclk-freq>—presets for Ethernet use cases. output_freq is the system PLL output frequency and refclk_freq is the system PLL reference clock frequency.
  • PCIE_FREQ_<output-freq>— presets for PCIe use cases. output_freq is the system PLL output frequency.
  • User configuration—manually configures output frequency of system PLL and selects one of the feasible reference clocks. For use in non PCIe use cases when other Ethernet presets do not meet requirement.
The default value is Disabled.
User configuration
User PCIE-based configuration
ETHERNET_FREQ_805_156
ETHERNET_FREQ_805_312
ETHERNET_FREQ_805_322 37.
ETHERNET_FREQ_830_156
ETHERNET_FREQ_830_312
ETHERNET_FREQ_830_312
PCIE_FREQ_1000
PCIE_FREQ_500
PCIE_FREQ_550
PCIE_FREQ_600
PCIE_FREQ_650
PCIE_FREQ_700
PCIE_FREQ_750
PCIE_FREQ_800
PCIE_FREQ_850
PCIE_FREQ_900
PCIE_FREQ_950
Reference clock source Reference clock #0 Selects the logical reference clock source for system PLL #1. The reference clock source can be shared with FGT PMA and other system PLLs.
Reference clock #1
Reference clock #2
Reference clock #3
Reference clock #4
Reference clock #5
Reference clock #6
Reference clock #7
Reference clock #8
Reference clock #9
Output frequency 31.25 to 1000 MHz Specifies the output frequency of the system PLL #1 in MHz. In background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, must specify the exact frequency with decimal points.
System PLL #2
Mode of system PLL 0, 1, 2 Selects the mode of system PLL #2.
  • Disabled— system PLL not used.
  • ETHERNET_FREQ_ <output-freq>_<refclk-freq>—presets for Ethernet use cases. output_freq is the system PLL output frequency and refclk_freq is the system PLL reference clock frequency.
  • PCIE_FREQ_<output-freq>— presets for PCIe use cases. output_freq is the system PLL output frequency.
  • User configuration—manually configures output frequency of system PLL and selects one of the feasible reference clocks. For use in non PCIe use cases when other Ethernet presets do not meet requirement.
  • User PCIe-based configuration— manually configures output frequency of system PLL and selects one of the feasible reference clocks. For use in PCIe use cases when PCIe presets do not meet requirement.
The frequency number in the Preset’s label are abbreviated, they are not full precise frequency.
User configuration
User PCIE-based configuration
ETHERNET_FREQ_805_156
ETHERNET_FREQ_805_312
ETHERNET_FREQ_805_322 37.
ETHERNET_FREQ_830_156
ETHERNET_FREQ_830_312
ETHERNET_FREQ_830_312
PCIE_FREQ_1000
PCIE_FREQ_500
PCIE_FREQ_550
PCIE_FREQ_600
PCIE_FREQ_650
PCIE_FREQ_700
PCIE_FREQ_750
PCIE_FREQ_800
PCIE_FREQ_850
PCIE_FREQ_900
PCIE_FREQ_950
Reference clock source Reference clock #0 Selects the logical reference clock source for system PLL #2. The reference clock source can be shared with FGT PMA and other system PLLs.
Reference clock #1
Reference clock #2
Reference clock #3
Reference clock #4
Reference clock #5
Reference clock #6
Reference clock #7
Reference clock #8
Reference clock #9
Output Frequency 31.25 to 1000 MHz Specifies the output frequency of the system PLL #2 in MHz. In background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, must specify the exact frequency with decimal points.
FHT Common PLL
Controller source Auto, CommonPLL A, CommonPLL B

If both common PLLs are enabled, this selection specifies the common PLL that drives the FHT microcontroller. The reference clock that drives this common PLL must be present and stable throughout F-tile operation.

FHT Common PLL A
Enable FHT Common PLL A On/Off Enable/Disable FHT common PLL A. When enabled, must provide FHT reference clock source and frequency. The default value is Off.
FHT reference clock source FHT reference clock #0 Specifies the logical reference clock source for FHT common PLL A. The default value is FHT reference clock #0.
FHT reference clock #1
FHT Common PLL B
Enable FHT Common PLL B On/Off When enabled, must provide FHT reference clock source and frequency. The default value is Off.
FHT reference clock source FHT reference clock #0 Specifies the logical reference clock source for FHT common PLL B. The default value is FHT Reference clock #0.
FHT reference clock #1
Reference clock(s)
FGT/System PLL
Enable reference clock #0 for FGT PMA On/Off Enables logical reference clock #0 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #0 25 to 380 MHz Specifies the reference clock #0 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #0 is shared between FGT PMA and system PLL, the parameter editor allows selection of calculated legal frequencies. The default value is 156.25 MHz.
Enable Reference clock #1 for FGT PMA On/Off Enables logical reference clock #1 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #1 25 to 380 MHz Specifies the reference clock #1 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA
When reference clock #1 is shared between FGT PMA and system PLL, reference clock frequency changes to drop-down of calculated legal frequencies and user must select one from drop-down. The default value is Disabled.
Enable Reference clock #2 for FGT PMA On/Off Enable logical reference clock #2 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #2 25 to 380 MHz Specifies the reference clock #2 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA
When reference clock #2 is shared between FGT PMA and system PLL, the parameter editor allows selection of calculated legal frequencies. The default value is Disabled.
Enable Reference clock #3 for FGT PMA On/Off Enable logical reference clock #3 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #3 25 to 380 MHz Specifies the reference clock #3 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA
When reference clock #3 is shared between FGT PMA and system PLL, the parameter editor allows selection of calculated legal frequencies. The default value is Disabled.
Enable Reference clock #4 for FGT PMA On/Off Enable logical reference clock #4 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #4 25 to 380 MHz Specifies the reference clock #4 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #4 is shared between FGT PMA and system PLL, , the parameter editor allows selection of calculated legal frequencies. The default value is Disabled.
Enable Reference clock #5 for FGT PMA On/Off Enable logical reference clock #5 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #5 25 to 380 MHz Specifies the reference clock #5 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #5 is shared between FGT PMA and system PLL, , the parameter editor allows selection of calculated legal frequencies. The default value is Disabled.
Enable Reference clock #6 for FGT PMA On/Off Enable logical reference clock #6 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #6 25 to 380 MHz Specifies the reference clock #6 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #6 is shared between FGT PMA and system PLL, , the parameter editor allows selection of calculated legal frequencies. The default value is Disabled.
Enable Reference clock #7 for FGT PMA On/Off Enable logical reference clock #7 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #7 25 to 380 MHz Specifies the reference clock #7 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #7 is shared between FGT PMA and system PLL, the parameter editor allows selection of calculated legal frequencies. The default value is Disabled.
Enable Reference clock #8 for FGT PMA On/Off Enable logical reference clock #8 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #8 25 to 380 MHz Specifies the reference clock #8 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #8 is shared between FGT PMA and system PLL, the parameter editor allows selection of calculated legal frequencies. . The default value is Disabled.
Enable Reference clock #9 for FGT PMA On/Off Enable logical reference clock #9 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off.
Reference clock frequency #9 25 to 380 MHz Specifies the reference clock #9 frequency. Range is:
  • 25 – 380 MHz when reference clock is configured for FGT PMA. (If using HDMI protocol, use only 25 – 100 MHz)
  • 100 – 380 MHz when reference clock is configured for System PLL or shared with system PLL and FGT PMA.
When reference clock #9 is shared between FGT PMA and system PLL, the parameter editor allows selection of calculated legal frequencies. . The default value is Disabled.
FGT CDR Clock-out(s)
Enable FGT CDR Output #0 On/Off Enables logical FGT CDR clock output #0. This must be enabled to configure FGT reference clock as a CDR clock output. The default value is Off.
Enable FGT CDR Output #1 On/Off Enables logical FGT CDR clock output #1. This must be enabled to configure FGT reference clock as a CDR clock output. The default value is Off.
FHT Reference clock(s)
FHT Reference clock frequency #0 100 to 200 MHz Specifies the FHT reference clock #0 frequency in MHz.
FHT Reference clock frequency #1 100 to 200 MHz Specifies the FHT reference clock #1 frequency in MHz.
37 This mode is not currently supported

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