F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.11.5. Lane Offset Address

FHT PMA

Lane offset address information is the offset for each lane in the FHT and FGT PMA Register Maps.

The following table shows the FHT PMA lane number to offset address mapping. Word address is byte address/4.

Table 77.   FHT PMA Lane Number and Offset Address
Lane Number Offset address (Byte address)
0 0x40000
1 0x48000
2 0x50000
3 0x58000

For example, if you need to access register address 0x45800 in the register map, add 0x8000 for each lane.

  • Lane0 -> 0x45800
  • Lane1 -> 0x4D800
  • Lane2 -> 0x55800
  • Lane3 -> 0x5D800

FGT PMA

The following table shows the FGT PMA offset address for each lane within a quad. Word address is byte address/4.

Table 78.   FGT PMA Lane Number and Offset Address
Lane Number Offset Address (Byte Address)
0 0x40000
1 0x48000
2 0x50000
3 0x58000
For example, if you need to update the TX equalizer co-efficients settings for the FGT PMA lanes within a quad, refer to the TX equalizer co-efficients offset register for lane 0 (0x47830) in the register map file and add 0x8000h for each incremental lane, as shown below.
  • Lane0 -> 0x47830
  • Lane1 -> 0x4F830
  • Lane2 -> 0x57830
  • Lane3 -> 0x5F830
Note: The 0x8000h incremental method to read lane 1, lane 2 and lane 3 information is not applicable for the 0xFFFFC register. Refer to F-Tile PMA/FEC Direct PHY Intel® FPGA IP Register Map for more information.
Note: If your design has more than four FGT PMA lanes that span across multiple FGT quads, refer to Logical Avalon Memory-Mapped Port Indexing.

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