F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP

To instantiate the F-Tile PMA/FEC Direct PHY Intel® FPGA IP:
  1. Specify the target device family, click Assignments > Device, and then select Agilex AGIB027R29A2E2V.
  2. If IP catalog is not already open, click View > IP Catalog in the Intel® Quartus® Prime software.
  3. In the IP Catalog search field, type f-tile pma, and double-click the F-Tile PMA/FEC Direct PHY Intel® FPGA IP .
    Figure 93.  F-Tile PMA/FEC Direct PHY Intel® FPGA IP in IP Catalog
  4. In the parameter editor, specify optional values to configure the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for your protocol implementation:
    You can optionally specify the FGT_NRZ_50G_2_PMA_Lanes_Custom_Cadence_ED in the collection of Presets to apply those default parameter values. During parameterization, instantiate the PMA direct channel. The available parameter editor options reflect your channel requirements.
  5. When parameterization is complete, click the Generate HDL button in the parameter editor to generate the IP instance and supporting files. Under Simulation, select Verilog and either VCS* or ModelSim* for Create simulation model.39
    Figure 94. Simulation Options
  6. Click the Generate button. Your IP variation RTL and supporting files generate according to your specifications, and are added to your Intel® Quartus® Prime project.

    The top-level file that generates with the IP instance includes all the available ports for your configuration. Use these ports to connect the F-Tile PMA/FEC Direct PHY Intel® FPGA IP to other IP cores in your design, as Connecting the F-tile PMA/FEC Direct PHY Design IP describes.

39 The current Intel® Quartus® Prime software version supports only VCS* or ModelSim* for F-tile simulation.

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