3.11.1. PMA and FEC Direct PHY Soft CSR Register Map
You must enable the Enable datapath Avalon® interface and the Enable Direct PHY soft CSR settings under the Datapath Avalon® Memory-Mapped Interface section in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP parameter editor to access the soft CSR registers. The datapath Avalon® memory-mapped reconfiguration space, starting from offset address 0x800h, contains the F-Tile PMA/FEC Direct PHY Intel® FPGA IP soft CSR registers.
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