F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP

The F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP is required only for dynamic reconfigurable designs, or if controlling multiple IP with one user interface for reconfiguration. The IP can access all tile registers in the F-tile for PMA setting reconfiguration.

You can use the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP to access nearly every IP register in the F-tile. To cover all the IP address spaces, you specify a page register inside the global Avalon® memory-mapped host. You must set the page register before entering the network.

Note: If you instantiate multiple F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP instances, the Compiler automatically instantiates an arbiter to handle signal arbitration.

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