F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021

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3.8.3. Reset Signals—Block Level

Table 73.  Reset Signals—Block Level
Reset Signal TX PHY TX Datapath RX PHY RX Datapath Soft CSRs
tx_reset Yes Yes No No No
rx_reset No No Yes Yes No
reconfig_xcvr_reset No No No No No
reconfig_pdp_reset No No No No Yes