F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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2.2.8.2. Bonded Lanes Use Case 2

One 200G-SR4 Ethernet MAC in Ethernet hard IP

  • Four PMA lanes at 53.125 Gbps per PMA lane
  • Modulation scheme: PAM4
  • Primary stream at EMIB_23
  • One st_x8 fracture is used

One 50 Gbps by three lanes in F-tile PMA and FEC Direct PHY IP

  • Three PMA lanes at 50 Gbps per PMA lane with FEC
  • Modulation scheme: PAM4
  • Primary stream at EMIB_15
  • Three st_x2 fractures are used

One 50G-CR1 Ethernet PCS in Ethernet hard IP

  • One PMA lane at 53.125 Gbps
  • Modulation scheme: PAM4
  • Primary stream at EMIB_7
  • One st_x2 fracture is used

One JESD204C by six lanes in F-tile PMA and FEC Direct PHY IP 6

  • Six PMA lanes at 32.0 Gbps per PMA lane without FEC
  • Modulation scheme: NRZ
  • Primary stream at EMIB_5
  • Six st_x1 fractures are used
Figure 38. Bonded Lanes Use Case 2The st_x2_7 fracture is reserved for 50 Gbps PMA and FEC Direct PHY IP. This fracture is associated with EMIB_8 and EMIB_9. This fracture and its associated EMIBs are unavailable to any other high-speed serial link IP. FGT2_Quad1, FGT0_Quad2, and all FHT PMA lanes are not available because there are no EMIBs available.
6 IP shown for illustrative purposes. Contact Intel FPGA support for specific IP availability.

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