F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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2.3.2.4. FGT PMA Loopback Modes

The PHY contains multiple parallel, serial data, and clock loopbacks across PHY interfaces for BIST. These loopbacks provide support for multiple PHY configurations.

Figure 45. FGT PMA Loopback ModesThe IP parameter editor does not currently support the loopback modes. Use register settings to specify loopback modes.
  • A. PMA-transmitter-to-receiver buffer loopback: loops back the transmitter pre-driver differential I/O signals to the midpoint of the receiver equalizer
  • B. PMA-transmitter-to-receiver parallel loopback: parallel loopback from the PMA transmit lane 64 bit data ports to the receive lane 64 bit data ports
  • C. PMA-receiver-to-transmitter parallel loopback: parallel loopback from the PMA receive lane 64 bit data ports to the transmit lane 64 bit data ports

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