F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP

The F-Tile Reference and System PLL Clocks Intel® FPGA IP is required IP for F-tile PMA/FEC Direct PHY designs.

F-Tile Reference and System PLL Clocks Intel® FPGA IP Overview

The F-Tile Reference and System PLL Clocks Intel® FPGA IP performs three main functions, each described below:

  • Configures the reference clock for FHT PMA:
    • Enable the FHT Common PLLs and select the reference clock source for FHT common PLL
    • Specify the FHT reference clock frequency
  • Configures the reference clock for FGT PMA:
    • Enable FGT reference clocks and specify the reference clock frequency
    • To enable FGT CDR Output (RX recovered clock output)
  • Configures the system PLL:
    • Enable system PLL and specify the mode
    • Specify the reference clock source and frequency for system PLL

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