F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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2.3.1.2.1. FHT Receiver Buffer and Equalizer

The receiver buffer receives serial data from input pins and feeds it to the CDR block and deserializer.

To optimize the bit error rate (BER) on every stream for optimum performance, receiver equalization is self-triggered, requires no input, and is independent of system initial conditions.

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