F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.8.9. Run-time Reset Sequence—TX with FEC

Figure 79. Run-time Reset Sequence—TX with FEC

As illustrated in the above figure, the following is the run-time reset sequence for TX with forward error correction (FEC):

  1. Assert tx_reset.
  2. tx_ready deasserts, indicating that the TX datapath is no longer operational.
  3. tx_reset_ack asserts, indicating that the TX datapath is fully in reset. You then deassert tx_reset to bring TX out of reset.
  4. tx_am_gen_start asserts, you then send at least two alignment markers on the tx_parallel_data bus.
  5. Assert tx_am_gen_2x_ack, indicating that at least two alignment markers have been sent.
  6. tx_am_gen_start deasserts, you then deassert tx_am_gen_2x_ack.
  7. tx_ready asserts.

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