F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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8.2.1. Modifying the Design to Enable F-Tile Transceiver Debug

To enable debugging capabilities, you must enable the Avalon® memory-mapped interface parameters in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP.

You can either activate these settings when you first instantiate the IP or modify the instances after preliminary compilation. Follow these steps to enable the settings:
  1. In the IP Components tab of the Project Navigator, right click the IP instance, and select Edit in Parameter Editor.
  2. Enable the datapath and PMA Avalon interface, Direct PHY soft CSR, and debug endpoint options under the Avalon® Memory-Mapped Interface tab as shown in the following figure.
    Figure 119. Parameters to Enable Transceiver Toolkit in F-Tile PMA/FEC Direct PHY Intel® FPGA IP
  3. Connect the reference signals that the debugging logic requires, if applicable. The debug endpoint requires clock and reset signal connections. For details on the how to connect these signals, refer to Configuring the F-Tile PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing.
  4. Click Generate HDL. After enabling parameters for all the IP instances in the design, recompile the project.

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