F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3.1.2. FHT Receiver PMA Architecture

The receiver recovers the clock information from the received serial data, deserializes the high-speed serial data, and creates a parallel data stream for either the receiver Ethernet hard IP, FEC block, or FPGA core.

Did you find the information on this page useful?

Characters remaining:

Feedback Message