F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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Document Table of Contents

3.3.3. RX Datapath Options

Figure 61. RX Datapath Options in Parameter Editor
Table 31.  RX FGT PMA Parameters
Parameter Values Description
Enable Gray coding On/Off Enables Gray coding. Applicable to PAM4 encoding only. When Off, link partner must send gray code set to 0xB4. When On, link partner must send gray code set to 0x6C. Must be Off for normal operation, or when in internal/external loopback mode). Default value is Off.
Enable precoding On/Off Enables precoding. Applicable to PAM4 encoding only. Default value is Off.
PRBS generator mode 23 disable, PRBS7, PRBS9, PRBS10, PRBS13, PRBS15, PRBS23, PRBS28, PRBS31, QPRBS13, PRBS13Q, PRBS31Q, SSPR, SSPR1, SSPRQ Enables hard PRBS generator with the PRBS polynomial selection. Default value is disable.
Enable SATA squelch detection On/Off Enables squelch detection for SATA. Default value is Off.
Enable fgt_rx_signal_detect port On/Off Enables the fgt_rx_signal_detect port. Default value is Off.
Enable fgt_rx_signal_detect_lfps port On/Off Enables the fgt_rx_signal_detect_lfps port. Default value is Off.
Enable rx_cdr_divclk_link0 port On/Off Enables the link port representing RX CDR clock output from RX PMA to the reference clock pin. The connection made from this port to the F-Tile Reference and System PLL Clocks Intel® FPGA IP guides the Fitter to determine the physical pin. Do not use this pin itself in simulation to observe clock behavior. Observe the actual clock behavior in the related output port of the F-Tile Reference and System PLL Clocks Intel® FPGA IP. The physical port is typically used for CPRI. You can connect the physical port to the physical reference clock pin 8 or 9 for configuration as RX CDR clock output. This setting is applicable for FGT PMA only. Default value is Off.
Selected rx_cdr_divclk_link0 source 0 to N-1, N = Number of PMA Lanes) Determines which RX FGT PMA lane is sourcing fgt_rx_cdr_divclk_link0. Note that FGT PMA index used in this parameter is logical. The selected PMA lane must be physically mapped to FGT Quad 3 (with reference clock 9) or FGT Quad 2 (with reference clock 8). If Enable rx_cdr_divclk_link0 port is off, this parameter is ignored. Default value is Off.
Enable rx_cdr_divclk_link1 port On/Off Enables the link port representing RX CDR clock output from RX PMA to the reference clock pin. The connection made from this port to the F-Tile Reference and System PLL Clocks Intel® FPGA IP guides the Fitter to determine the physical pin. Do not use this pin itself in simulation to observe clock behavior. Observe the actual clock behavior in the related output port of the F-Tile Reference and System PLL Clocks Intel® FPGA IP. The physical port is typically used for CPRI. You can connect the physical port to the physical reference clock pin 8 or 9 for configuration as RX CDR clock output. This setting is applicable for FGT PMA only. Default value is Off.
Selected rx_cdr_divclk_link1 source 0 to N-1 N = Number of PMA Lanes) Determines which RX FGT PMA lane is sourcing fgt_rx_cdr_divclk_link1. Note that FGT PMA index used in this parameter is logical. The selected PMA lane must be physically mapped to FGT Quad 3 (with reference clock 9) or FGT Quad 2 (with reference clock 8). If Enable rx_cdr_divclk_link1 port is off, this parameter is ignored. Default value is Off.
Enable fgt_rx_set_locktoref port On/Off Asserting this signal keeps CDR in lock to reference mode. Deasserting this signal keeps CDR in auto mode. When switching modes, assert reset. In manual reference clock mode, switch the reset controller to ignore locktodata mode through appropriate write to soft CSRs. Default value is Off.
Enable fgt_rx_cdr_freeze port On/Off

This port is for GPON to freeze the CDR lock state during non-active time-slots. Default value is Off.

RX FGT CDR Settings
Output frequency 12890.625MHz Specifies the non editable RX FGT CDR output frequency initial value derived from the IP configuration.
VCO frequency 12890.625MHz Specifies the non editable RX FGT CDR VCO output frequency initial value derived from the IP configuration.
RX FGT CDR reference clock frequency 25.781250-250.000000 Selects the reference clock frequency (MHz) for CDR. Default value is 156.25.
RX User Clock Setting
Enable RX user clock On/Off Divider values of RX CDR output frequency. If the clock is not used, you can disable the clock to save power. This clock source drives both RX User Clock1 and User Clock 2 in the Core Interface. Default value is Off.
RX user clock div by 12- 139.5 Division factor from Fvco of RX CDR to RX user clock. Values from 12 to 139.5 are acceptable in 0.5 increments. Default value is 100.
Figure 62. RX FHT PMA Parameters in Parameter Editor
Table 32.  RX FHT PMA Parameters
Parameter Values Description
Enable FHT RX PAM4 Level Alternative Coding On/Off Enable this for RX PAM4 Level Alternative Coding. When disabled, link partner must send gray code set to 0xB4. When enabled, link partner must send gray code set to 0x6C. You must disable this parameter for normal operation or when in internal or external loopback. Default value is Off.
Enable FHT RX P&N Invert Disabled/Enabled Enable this to invert RX P and N input. Default is Disabled.
Enable FHT RX data profile Disabled/Enabled Enable FHT RX data profile to set the threshold for number of 1’s in 1M RX Data bits that determine the quality of RX data. If the number of 1's received is not within the specified min and max threshold, then RX bad status is indicated. You determine the threshold minimum and maximum based on your data and specify it in FHT RX data 1 count maximum and FHT RX data 1 count minimum parameters described below. Default is Disabled.
Note: This parameter must be Enabled.
FHT Rx data 1 count maximum 550000 Selects high threshold of 1s in 1M RX data bits. Default is 550000. Recommended value is 550000. Must be used in conjunction with the Enable FHT RX data profile parameter.
FHT Rx data 1 count minimum 450000 Selects low threshold of 1s in 1M RX data bits. Default is 450000. Recommended value is 450000. Must be used in conjunction with the Enable FHT RX data profile parameter.
FHT RX user clk div33_34 select

RX_DIV_33

RX_DIV_34

RX_DIV_66

RX_DIV_68

Selects one of the four DIV clock output for the RX user clock. Refer to Clocking. Default is RX_DIV_66.
Enable FHT RX pre-encoder On/Off Enables FHT TX pre-encoder. Default value is off. This setting must match the link partner's RX pre-encoder setting.
Enable FHT RX user clk1 On/Off Enables FHT RX user clk1. Default is Off.
FHT RX user clk1 select

DIV3334

DIV40

FHT RX user clk1 select. Off selects div3334 (one of the four DIV clocks listed in user div33_34). On selects DIV40 clock. Refer to Clocking. Default is div3334.
Enable FHT RX user clk2 On/Off Enables FHT RX user clk2. Default value is Off.
FHT RX user clk2 select

DIV3334

DIV40

FHT RX user clk2 select. Off selects div3334 (one of the four DIV clocks listed in user div33_34). On selects DIV40 clock. Refer to Clocking. Default is div3334.
23

The PRBS31, QPRBS13, PRBS13Q, PRBS31Q, SSPR, SSPR1, and SSPRQ PRBS generator mode settings are not currently supported through the IP GUI, although present in the parameter editor. Do not select any of the unsupported PRBS generator mode settings. Specify these settings using registers.

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