F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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5.3. Hardware Flow Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP

You can access the FHT and FGT PMA registers using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP.

Here are the steps you need to follow to add the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP to work with a F-Tile PMA/FEC Direct PHY Intel® FPGA IP design.

  1. Add the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP into your design and enable the read_data_valid port as shown in the following figures.
    Figure 86. F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP
    Figure 87.  F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP Settings
  2. Add the JTAG to Avalon® Master Bridge Intel FPGA IP into your design.
    Figure 88. JTAG to Avalon® Master Bridge Intel FPGA IP
  3. Declare wires to connect the g_avmm interface to the jtag_master ports as shown in the following figure.
    Note: The g_avmm_address port of g_avmm interface is 18 bits and the master_address port of jtag_master is 32 bits.
    Note: You need to enable the readdatavalid port in the JTAG to Avalon® Master Bridge Intel FPGA IP and connect it to the corresponding F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP port.
    Figure 89.  F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP to JTAG to Avalon® Master Bridge Intel FPGA IP RTL Connections
  4. In the F-Tile PMA/FEC Direct PHY Intel® FPGA IP, disable both the datapath Avalon® interface and the PMA Avalon® interface by unchecking the interfaces as shown in the following figure.
    Note: This step is optional. The datapath and PMA Avalon® interface in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP and the Global Avalon® memory-mapped interface can function together.
    Figure 90. Disable Datapath and PMA Avalon® Interface in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
  5. Run the Support-Logic Generation for your design in the Intel® Quartus® Prime Pro Edition software and place the F-tile in your design by using the Tile Interface Planner tool as shown in the following figure. Refer to F-tile Interface Planning for more information.
    Figure 91. Using Tile Interface Planner to Obtain the F-Tile Co-ordinates
    Once you have the F-tile co-ordinates add the following assignment in your qsf settings file.

    set_instance_assignment -name IP_TILE_ASSIGNMENT <F-tile co-ordinates> -to gavmm_inst

    For example you must add the following assignment in your qsf settings file for the AGIB027R29A1E2VR0 device.

    set_instance_assignment -name IP_TILE_ASSIGNMENT Z1577A_X0_Y0_N0 -to gavmm_inst

    Note: The gavmm_inst qsf assignment name must be identical to the instance name in your design file or else you can get a placement failure in the design compilation.
  6. To perform hardware testing to access registers using the global Avalon® interface you need to do the following:
    • Write the page address of the block you want to access to the page address: 0xffffc. The following table shows the page address of the various blocks in the F-tile.
      Table 94.  Block and Page Address
      Block Page Address
      EMIB 0x00
      400G Hard IP 0x02
      400G 0x04
      200G Hard IP 0x06
      200G FEC/PMA Interface 0x08
      PCIe Hard IP 0x0A
      FGT PMA Quad 0 0x0C
      FGT PMA Quad 1 0x0D
      FGT PMA Quad 2 0x0E
      FGT PMA Quad 3 0x0F
      FHT PMA 0x10
    • You can then read and write values to the PMA offset register address to access the registers.

      As an example, here are steps to access the registers in a FGT PMA in quad 3 for a one channel 25G design.

      1. Read address 0xffffc; it should be 0x00000000.
      2. Write 0xf to address 0xffffc.
      3. Read address 0xffffc; it should be 0x0000000f.
      4. Now you can read the various offset address registers to access the register values. In this example, you can read address 0xf0010, 0x40740, and 0x62000 and get their register values.

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