F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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2.3.1.1.4. FHT Data Pattern Generator and Verifier

The data pattern generator is a design-for-test feature for generating PHY data traffic. This feature allows you to debug the PMA without involving the upper protocol hard IP layers. F-tile has a pseudo-random binary sequence (PRBS) pattern generator on the PMA which operates in all bit modes and can generate several patterns. The pattern and size are programmable.

There are patterns supporting both NRZ and PAM4. PRBS NRZ patterns are different from PAM4 patterns. For the same setting, depending on the encoding mode, either PRBSx (NRZ) or PRBSxQ (PAM4) is configured. Different specifications such as CEI OIF and IEEE 803.2 refer to quaternary PAM4 patterns differently. For example, QPRBS13 is identical to PRBSQ13 and QPRBS31 is identical to PRBSQ31.

Table 15.  Supported Programmable PRBS Patterns by Mode
NRZ Mode PAM4 Mode

PRBS7

PRBS9

PRBS11

PRBS13

PRBS23

PRBS318

PRBS58

PRBS7Q

PRBS9Q

PRBS11Q

PRBS13Q

PRBS23Q

PRBS31Q

PRBS58Q

User-defined pattern (32 bit, 64 bit, or 128 bit)
Alternating 0s and 1s pattern (repeat one, eight, or 64 times)

The data pattern verifier functions like the generator.

8

The PRBS31, QPRBS13, PRBS13Q, PRBS31Q, SSPR, SSPR1, and SSPRQ PRBS generator mode settings are not currently supported through the IP GUI, although present in the parameter editor. Do not select any of the unsupported PRBS generator mode settings. Specify these settings using registers.

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