F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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Document Table of Contents

10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide

Document Version Intel® Quartus® Prime Version Changes
2021.12.15 21.4 Made the following changes:
  • Updated Increment and Decrement Size column in the FGT Transmitter PMA Equalizer Parameters for NRZ and PAM4 Modes table.
  • Added footnote for System PLL frequency description in General and Common Datapath Options table.
  • Added footnote for TX FGT PLL reference clock frequency description in TX FGT Datapath Parameters table.
  • Added footnote to TX and RX Reference Clock and Clock Output Interface Signals table.
  • Removed note for Enable rx_cdr_divclk_link0 port and Enable rx_cdr_divclk_link1 port parameters in the RX FGT PMA Parameters table.
  • Updated Example Design Generation with RS-FEC example design information.
  • Added note to Clocking section in Implementing the F-Tile PMA/FEC Direct PHY Intel FPGA IP chapter.
  • Added RX invert P and N, RX termination, TX invert P and N, TX termination, TX out tristate enable and TX equalization qsf settings for FHT PMA in Configurable Intel Quartus Prime Software Settings section.
  • Removed RX termination mode select qsf setting for FGT PMA in Configurable Intel Quartus Prime Software Settings section.
  • Added TX equalization qsf setting for FGT PMA in Configurable Intel Quartus Prime Software Settings section.
  • Updated steps 4a, 6, 8a, 10c, 13c, 14b and 14c in the FGT Attribute Access Method Example topic.
  • Reorganized information in the Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP chapter to make it more clear.
  • Removed note for Enable FGT CDR Output #0 and Enable FGT CDR Output #1 parameters in the F-Tile Reference and System PLL Clocks Intel FPGA IP Parameters table.
  • Added description to specify qsf location assignment for the out_cdrclk_i port in the F-Tile Reference and System PLL Clocks Intel FPGA IP Port List table.
  • Added new section Guidelines for F-Tile Reference and System PLL Clocks Intel FPGA IP Usage.
  • Updated step 5 of the Hardware Flow Using the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP section.
  • Updated F-tile PMA/FEC Direct PHY Design Implementation chapter to remove references to design example.
  • Updated F-Tile Transceiver Toolkit GUI, Collection View Tab of the F-Tile Transceiver Toolkit GUI, Toolkit Explorer, Example BER Test Setup and Results for the FGT PMA figures in the Debugging F-Tile Transceiver Links chapter.
  • Updated PMA naming in the Running BER Tests section.
  • Updated Transceiver Toolkit Parameter Settings table with new information.
  • Updated Creating Transceiver Links section with Import Collections and Export Collections details.
  • Added footnote for TX Equalization Parameters in the Transceiver Toolkit Parameter Settings table.
2021.10.15 21.3 Made the following changes:
  • Updated the Preserving Unused PMA Lanes section.
  • Updated the Number of system copies parameter in General and Common Datapath Options table.
  • Added Enable Core PLL mode parameter in TX FGT Datapath table.
  • Updated Enable FHT RX data profile parameter in RX FHT PMA Parameters table.
  • Updated the Example Design Generation topic in the Configuring the IP section.
  • Updated parameter names to match with GUI names in Avalon® Memory Mapped Interface Parameters table.
  • Added description for Number of system copies parameter in the Signal and Port Reference section.
  • Updated description of the FGT PMA Fractional Mode section.
  • Added new topic Run-time Reset Sequence Approximate Time Duration in Run-time Reset Sequence—TX + RX section.
  • Updated step 4 onwards in the Run-time Reset Sequence—TX with FEC section
  • Updated description of the Lane Offset Address section.
  • Added new topic Logical Avalon Memory-Mapped Port Indexing in Configuration Registers section.
  • Updated steps in FGT Attribute Access Method Example.
  • Added footnote that ETHERNET_FREQ_805_322 is not supported in section Mode of System PLL - System PLL Reference Clock and Output Frequencies.
  • Added new section Hardware Flow Using the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP in Implementing the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP chapter.
  • Added the following new sections in the F-tile PMA/FEC Direct PHY Design Example Implementation chapter.
    • Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel FPGA IP.
    • PAM4 Encoding Schemes in Simulation.
    • F-tile Interface Planner Design Example.
    • Updated the Simulating the F-tile PMA/FEC Direct PHY Design Example section.
  • Added and updated the following sections in the Supported Tools chapter.
    • F-Tile PMA and FEC Direct Port Mapping Calculator.
    • F-Tile Clocking and Datapath Tool.
    • F-Tile TX Equalizer Tool.
  • Added new chapter Debugging F-Tile Transceiver Links.
2021.08.18 21.2
  • Added the following new sections and updated table in Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP chapter:
    • Configuration Registers.
    • Configurable Intel® Quartus® Prime Software Settings.
    • Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing.
    • Hardware Configuration Using the Avalon® Memory-Mapped Interface.
    • Added loopback mode in TX FHT PMA Parameters table.
  • Added new topic in F-Tile Placement Rules section in the F-Tile Architecture chapter:
    • Preserving Unused PMA Lanes.
  • Added new chapter Supported Tools.
  • Added new chapter Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide.
    • Consolidated the Document Revision History section of each chapter into this chapter.
2021.07.23 21.2 Updated tx_am_gen_start and tx_am_gen_2x_ack signal directions in the following tables:
  • Reset Signals table.
  • Reset Signal Descriptions table.
2021.06.24 21.2 Initial document release.

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