F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.4.2. TX and RX Reference Clock and Clock Output Interface Signals

Table 39.  TX and RX Reference Clock and Clock Output Interface SignalsRefer to Table 1 for variable definitions.
Signal Name Clocks Domain/Resets Direction Description

rx_clkout [(N*X)-1:0]

rx_clkout2 [(N*X)-1:0]]

tx_clkout [(N*X)-1:0]

tx_clkout2 [(N*X)-1:0]

N/A output Refer to Clock Ports
tx_coreclkin [N*X-1:0] N/A input The FPGA core clock. Drives the write side of the TX FIFO.
rx_coreclkin [N*X-1:0] N/A input The FPGA core clock. Drives the read side of the RX FIFO.
tx_pll_refclk_link [N-1:0] 24 N/A input This is neither physical nor logical pin. You connect this to <out_refclk_fgt_<X> > port from the F-Tile Reference and System PLL Clocks Intel® FPGA IP 25.
rx_cdr_refclk_link [N-1:0] N/A input This is neither physical nor logical pin. You connect this to <out_refclk_fgt_<X> > port from the F-Tile Reference and System PLL Clocks Intel® FPGA IP 25.
system_pll_clk_link N/A input This is neither physical nor logical pin. You connect this to <out_systempll_clk_0 > port from the F-Tile Reference and System PLL Clocks Intel® FPGA IP 25.
tx_pll_locked [N-1:0] asynchronous output TX PLL locked signal for both FGT and FHT to reference clock within the PPM threshold status signal. 1’b1 = locked. 1’b0 = not locked.
rx_cdr_divclk_link0 N/A output Clock output from FGT CDR divided clock. This signal is used for CPRI. F-tile includes a total of two such pins. This port is neither physical nor logical pin. If you enable, you must set the number of system copies to 1. This port must connect to the out_cdrclk port of the F-Tile Reference and System PLL Clocks Intel® FPGA IP . This port cannot be enabled in a quad that has primary PLL configuration25.
rx_cdr_divclk_link1 N/A output Clock output from FGT CDR divided clock. This signal is used for CPRI. In whole F tile, there are 2 of such pins. This port is neither physical nor logical pin. If you enable this port, you must set number of system copies to 1. This port must connect to the out_cdrclk port of F-Tile Reference and System PLL Clocks Intel® FPGA IP. You cannot enable a quad that has primary PLL configuration in PLL cascade mode. Not supported for FHT25.
24 Ports ending in "_link" must connect to the F-Tile Reference and System PLL Clocks Intel® FPGA IP. These ports cannot be simulated.
25 Refer to Guidelines for F-Tile Reference and System PLL Clocks Intel FPGA IP Usage for reference clock and system PLL usage.

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