F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.7.2. Rate Match FIFO

When using the system PLL clocking mode, you must create and instantiate a rate match FIFO in PMA/FEC Direct mode when the user FPGA core logic (user clock domain) runs at a different frequency than system PLL frequency (system PLL frequency ÷ 2 when double width transfer is enabled). You must create and implement this rate match FIFO for the clock domain transfer from the user clock domain to the system PLL clock domain.

As the rate match FIFO is not available in IP catalog, you must create the FIFO. Implement the FIFO by placing a rate-matching soft FIFO between your logic and the core for pacing the data valid signal. Use this technique whenever the user FPGA core logic (user clock domain) runs at a different frequency than system PLL frequency (system PLL frequency ÷ 2 when double width transfer is enabled).

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