2.1.5. PCIe* Hard IP
The F-tile PCIe* hard IP consists of four PCIe* cores: one x16 (core_0), one x8 (core_1) and two x4 (core_2, core_3). It consists of a set of port bifurcation muxes to remap the four controller PHY interface for PCI Express* (PIPE) lane interfaces to the shared 16 FGT lanes. core_0 can be configured to support x16, x8, and x4 configurations, and core_1 can be configured to support x8 and x4 configurations. core_2 and core_3 only support only x4 configurations.
|1x PCIe* x16||Root port or endpoint and upstream or downstream port|
|2x PCIe* x8||
|1x PCIe* x8||Root port or endpoint|
|4x PCIe* x4||Root port only and upstream or downstream port|
|2x PCIe* x4||Root port only|
|1x PCIe* x4||Endpoint only|
|Mode||Transaction Layer||Data Link Layer||PHY Layer|
|Full hard IP||Yes||Yes||Yes|
|Transaction layer packet (TLP) bypass||Yes (Lite)||Yes||Yes|
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