F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode

The following data is specific to the X=2 case for a FEC Direct mode. N indicates the number of PMA lanes. For a given N, n can be from 0 --> N-1. N can be up to 8 for FGT, and up to 4 for FHT, and depends on the number of PMA lanes. Enable Double width transfer Enabled = 1. Refer to Table 1 for full variable definitions.

Table 63.  Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
  Bits TX Parallel Data for n-0 Bits TX Parallel Data for n=1 .. Bits TX Parallel Data for n=7
Second Stream 157 TX Alignment marker 317 TX Alignment marker 1277 TX Alignment Marker
152:120 TX Data(Upper 33 bits) 312:280 TX Data (Upper 33 bits) 1272:1240 TX Data (Upper 33 bits)
118 TX PMA Interface Data Valid Bit 278 TX PMA Interface Data Valid Bit .. 1238 TX PMA Interface Data Valid Bit
117 TX Alignment Marker 277 TX Alignment Marker 1237 TX Alignment Marker
112:82 TX Data (Lower 31 bits) 272:242 TX Data (lower 31 bits) 1232:1202 TX Data (Lower 31 bits)
81:80 Sync Head

241:240

Sync Head

1201:1200 Sync Head
First Stream 77 TX Alignment Marker 237 TX Alignment Marker 1197 TX Alignment Marker

72:40

TX Data

(Upper 33

Bits)

232:200 TX Data(upper 33 bits) 1192:1160 TX Data (upper 33 bits)
38 TX PMA Interface Data Valid Bit 198 TX PMA Interface Data Valid Bit .. 1158 TX PMA Interface Data Valid Bit
37 TX Alignment Marker 197 TX Alignment Marker 1157 TX Alignment Marker
32:2 TX Data (Lower 31 bits) 192:162 TX Data(Lower 31 bits) 1152:1122 TX Data(lower 31 bits)
1:0 Sync Head 161:160 Sync Head 1121:1120 Sync Head

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