F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021

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6. F-tile PMA/FEC Direct PHY Design Implementation

This chapter describes the IP parameterization, PHY IP connections, simulation, and tile placement planning for a F-tile PMA/FEC Direct PHY design. The design implements two 25.78125 Gbps NRZ PMA Direct FGT lanes, with a throughput of 51.5625 Gbps, and with system PLL datapath clocking mode.