F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021

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2.4.3. System PLL

F-tile has three on-board system PLLs. These system PLLs are the primary clock source for hard IP (MAC, PCS, and FEC) and EMIB crossing. This means that, when you use the system PLL clocking mode, the blocks are not clocked by the PMA clock and do not depend on a clock coming from the FPGA core. Each system PLL only generates the clock associated with one frequency interface. For example, you need two system PLLs to run one interface at 1 GHz and one interface at 500 MHz. Using a system PLL allows you to use every lane independently without a lane clock change affecting a neighboring lane.

Each system PLL can use any one of eight FGT reference clocks. System PLLs can share a reference clock or have different reference clocks. Each interface (hard IP) can choose which system PLL it uses, but, once chosen, it is fixed, not reconfigurable using dynamic reconfiguration. If PMA Direct PHY IP uses the system PLL clocking mode, PMA Direct is a data valid type interface.

With three system PLLs, you can use, for example, one system PLL for PCIe* and two for Ethernet and other protocols. However, there are other use cases, and you can use all three for various interfaces within the Ethernet and PMA Direct digital blocks. Because there are only three system PLLs, multiple hard IPs with different line rates may have to share a system PLL. When multiple hard IPs share a system PLL, the hard IP with highest line rate determines the system PLL frequency, and the hard IPs with the lower line rates must be overclocked. The exact cadence is based on the clock; see Datapath Clock Cadences for details.

The following table shows an example where four interfaces share a system PLL:

  • The system PLL is native for the 50GbE datapath interface (the highest line rate of all four interfaces).
  • The three lower line rate datapath interfaces are overclocked and need custom cadence.
Table 22.  Example of a Single System PLL Shared Between Interfaces
Design Line Rate (Gbps) PMA Width PMA Clock Frequency (MHz): Line Rate ÷ PMA Width System PLL Frequency (MHz) System PLL Output-to-Core Frequency (MHz) Datapath Clock Frequency
50GbE 53.125 64 830.08 830.08 415.04 Same as the PMA clock frequency
25GbE 25.78125 32 805.67 830.08 415.04 Over-clocked to the PMA clock frequency
24G CPRI 24.33024 32 760.32 830.08 415.04 Over-clocked to the PMA clock frequency
9.8G CPRI 9.8304 20 491.52 830.08 415.04 Over-clocked to the PMA clock frequency

Use the F-Tile Clocking Tool to visualize how IP and tile settings impact the datapath clocking mode. Start by reading the tool’s Introduction tab.

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