8.3. Transceiver Toolkit Parameter Settings
|Auto refresh RX CDR status||Enable this option to update the RX CDR status real time.||Receiver pane.|
|Auto refresh RX PMA settings||Enable this option to update the RX Equalization settings real time for FGT PMA.||Receiver pane.|
|Auto refresh TX Status||Enable this option to update the TX PLL lock status real time.||Transmitter pane|
|Bit error rate (BER)||Reports the number of errors divided by bits tested since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable.||Receiver pane|
|Clear Stats||Clear the current number of bits tested, number of error bits and BER.||Receiver pane|
|Hard PRBS checker running||
Red: checker stops.
Green: checker is checking, and data pattern is locked.
|Hard PRBS generator running||
Red: generator stops.
Green: generator is sending a pattern.
|Inject Error||Inject a bit error in the transmitter PRBS pattern.||Transmitter pane|
|Line encoding||Specifies the modulation type used for serial data.||Transmitter and receiver pane|
|Loopback mode||Select the loopbacks mode. The available options are:
||Transmitter and receiver pane|
|Number of bits tested||Specifies the number of bits tested since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable||Receiver pane|
|Number of error bits||Specifies the number of error bits encountered since the last reset of the checker. When RX CDR is locked to reference clock or PRBS checker is not locked, the BER reported is not reliable||Receiver pane|
|PRBS locked||Green: indicates the PRBS checker is locked to the received PRBS pattern.||Receiver pane|
|PRBS pattern||Select the test pattern for the bit error test.||Transmitter and receiver pane|
|RX CDR locked to ref clock||Green: Indicates the receiver in lock-to-reference (LTR) mode.||Receiver pane|
|RX CDR locked to data||Green: Indicates the receiver in lock-to-data (LTD) mode.||Receiver pane|
|RX Enable Gray Code||Enables Gray coding for PAM4 only.||Receiver pane|
|RX PMA Settings||RX Equalization settings. There are read-only values. Manual control of the settings in FGT are planned in a future version.||Receiver pane|
|RX Polarity Inversion||Enable RX polarity inversion.||Receiver pane|
|RX Ready||Green: RX channel out of reset.||Receiver pane|
|RX Reset FGT PMA||Reset the FGT RX datapath.
Note: Clicking the RX reset of one channel resets all the RX channels in the same F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance.
|Start||Starts the pattern generator or checker on the channel to verify incoming data.||Transmitter and receiver pane|
|Stop||Stops generating patterns and testing the channel.||Transmitter and receiver pane|
|TX Enable Gray Code||Enables Gray coding for PAM4 only.||Transmitter pane|
|TX Equalization Parameters||FGT 41||FHT 42 43||Transmitter pane and receiver pane|
M1: Post-cursor 1
C0: Main cursor
P1: Pre-cursor 1
P2: Pre-cursor 2
M3: Pre-cursor 3
M2: Pre-cursor 2
M1: Pre-cursor 1
C0: Main cursor
P1: Post-cursor 1
P2: Post-cursor 2
P3: Post-cursor 3
P4: Post-cursor 4
|TX PLL Locked||Green: Indicates TX PLL locks to reference clock.||Transmitter pane|
|TX Polarity Inversion||Enable TX polarity inversion.||Transmitter pane|
|TX Reset FGT PMA||Reset the FGT TX PMA datapath.
Note: Clicking the TX reset of one channel resets all the TX channels in the same F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance.