F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2.2. Setting TX Datapath Options

Specify options for the following on the F-Tile PMA/FEC Direct PHY Intel® FPGA IP parameter editor TX Datapath Options tab:

  • TX FGT PMA
  • TX FGT PLL
  • TX datapath FIFO modes

The design specifies the following TX Datapath Options:

Table 96.  TX FGT PLL Options
Parameter Parameter Value
TX FGT PLL reference clock frequency Select 156.25MHz. The TX FGT PLL reference clock frequency must match the reference clock frequency that the F-Tile Reference and System PLL Clocks Intel® FPGA IP specifies, as Figure 97 shows. To connect the out_refclk_fgt_0 to this IP, refer to Connecting the F-tile PMA/FEC Direct PHY Design IP
Figure 97. TX FGT PLL Settings
Table 97.  TX PMA Interface Options
Parameter Parameter Value
TX PMA interface FIFO mode Elastic
Enable custom cadence generation ports and logic

Generates the tx_cadence port that you can use to assert and de-assert the PMA data valid bit. This option is needed because the system PLL frequency is greater than the PMA clock frequency in this design. Refer to Custom Cadence Generation Ports and Logic.

TX core Interface FIFO Mode Phase Compensation
TX tile FIFO Interface FIFO Mode Phase Compensation
Enable TX double width transfer On. When On, you must drive the tx_clkout source with Sys PLL Clk Div2 source instead of sys PLL clk source. Divide the core clocking frequency by two to avoid exceeding the maximum EMIB to core frequency specification.
Figure 98. TX PMA Interface Options

Did you find the information on this page useful?

Characters remaining:

Feedback Message