F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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2.4.1.3. FGT Primary PLL Configuration

A primary PLL configuration is when the TX PLL of one lane is in fractional mode and acts as the reference clock source for the local CDR and TX PLL and RX CDR blocks of other lanes (configured in integer mode) within the quad. There are two different primary PLL configurations: quad and pair. These three configurations are the only supported lane combinations for a primary PLL configuration.

In a quad configuration, FGT3 is always the primary. For example, in Quad3, FGT3_Quad3 is the primary, and the FGT3_Quad3 TX PLL output is the reference clock for the FGT3_Quad3 RX, FGT2_Quad3, FGT1_Quad3, and FGT0_Quad3 TX PLL, and RX CDR.

In a pair configuration with only two PMAs combined, FGT3 or FGT1 can be the primary. For example, when using FGT3_Quad3 and FGT2_Quad3, FGT3_Quad3 is the primary, and the FGT3_Quad3 TX PLL output is the reference clock for the FGT3_Quad3 RX, FGT2_Quad3 TX PLL, and RX CDR. If using FGT1_Quad3 and FGT0_Quad3 , FGT1_Quad3 is the primary.

Figure 48. FGT Primary PLL Configurations

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