F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.11.4. FEC Register Map

The FEC Register Map is part of the F-Tile Ethernet Intel® FPGA Hard IP Register Map.

You must Enable datapath Avalon® interface setting under the Datapath Avalon® Memory-Mapped Interface section in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP parameter editor to access the FEC registers. In the F-Tile Ethernet Intel® FPGA Hard IP Register Map, you can filter the Module/Feature column to select FEC to view the FEC registers.

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