F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.7.1. Enabling the tx_cadence_slow_clk_locked Port

If the tx_cadence_slow_clk signal does not come directly from TX PLL (word clock, bond clock, user clock), but rather comes from the other clock source (as might be applicable in FEC Direct modes when using slower clock to accommodate FEC overhead), you must enable the tx_cadence_slow_clk_locked port in the IP parameter editor. The PLL locked output of the other clock source used for slow clock must drive tx_cadence_slow_clk_locked.

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