F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021

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3.8.8. Run-time Reset Sequence—TX + RX

Figure 78. Run-time Reset Sequence—TX + RX

The figure above illustrates the following run-time TX - RX reset sequence:

  1. Assert tx_reset and rx_reset.
  2. Tx_ready and rx_ready deassert, indicating that datapaths are no longer operational.
  3. Tx_reset_ack and rx_reset_ack assert, indicating that the core is fully in reset.
  4. You then deassert tx_reset and rx_reset.
  5. The system is fully out of reset, tx_ready and rx_ready assert, indicating the TX/RX datapaths are ready for use.
  6. Tx_reset_ack and rx_reset_ack deassert.