F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

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3.6.4. FGT PMA Fractional Mode

For a given data rate, the drop-down menu lists the supported integer mode reference clock frequencies. For a given data rate, if the required reference clock frequency is not listed in the drop-down, you can either select one of the supported integer mode reference clock frequencies or enable fractional mode.

  • When enabling fractional mode, if exact fraction is not available (K = 0.25,0.5, 0.75), use 140MHz reference clock frequency for approximate fractional mode.
  • To calculate K, divide k value displayed in the IP GUI system messages; K = k / 2^22. For example, for k = 2097152, K = 0.5.
  • For a given data rate, you must enable fractional mode if you need to dynamically configure the K value during run time. When you enable fractional mode, you must enter the TX FGT PLL fractional mode reference clock frequency.

FGT PMA supports fractional mode in following PMA modes:

Table 70.  FGT PMA Support for Fractional Mode
PMA Mode Fractional Mode Support
TX simplex TX FGT PLL supports fractional mode in TX simplex. To enable, select TX simplex option for PMA mode, and turn on the Enable TX FGT PLL fractional mode in the parameter editor. The TX PLL fractional counter values automatically calculate for the selected reference clock frequency. You can place TX Simplex fractional mode on any of 16 FGT TX PMAs.
Note: FGT PMA does not support fractional mode for RX simplex.
Duplex FGT PMA in Duplex PMA mode supports fractional mode. To enable fractional mode in duplex PMA mode, select the Duplex option for PMA mode, select 16 for the Number of PMA lanes, and turn on Enable TX FGT PLL fractional mode option in the parameter editor.
  • In Duplex fractional mode, the output of each TX PLL is used as the reference clock for corresponding RX CDR. Each TX PLL is configured as fractional mode.
  • A separate reference clock is not required for RX CDR. TX PLL fractional counter values, and RX CDR reference clock frequency, automatically calculate for the selected reference clock frequency.
  • You can place duplex fractional mode on any of 16 FGT PMAs.
Primary PLL configuration To enable fractional mode with the primary PLL configuration, select the Duplex option for PMA mode, select 2 or 4 for the Number of PMA lanes, and turn on Enable TX FGT PLL fractional mode and Enable TX FGT PLL cascade mode options in the parameter editor.
  • In Primary PLL configuration, the TX PLL of one lane is in fractional mode and acts as the reference clock source for the local CDR and TX PLL and RX CDR blocks of other lanes (configured in integer mode) within the quad.
  • Primary PLL configuration is not supported when you select 6 ,8, 12, or 16 for the number of PMA lanes.
  • You can place the primary PLL configuration with 2 PMA lanes either on FGT PMA Lane 1 and 0 (same quad) of any quad, with Lane 1 as the primary. On FGT PMA Lane 3 and 2 (same quad) of any quad with lane 3 being the primary.
  • You can place the primary PLL configuration with 4 PMA lanes on FGT PMA Lane 3,2,1 and 0 (same quad) of any quad with Lane 3 being the primary.
  • When you place any primary PLL configuration in Quad 2, you cannot configure reference clock [8] (accessible by Quad2) as output to provide RX recovered clock.
  • When you place any primary PLL configuration in Quad 3, you cannot configure reference clock [9] (accessible by Quad3) as output to provide RX recovered clock.
Note: Refer to FGT PLL Configuration in F-tile Architecture User Guide for more information.

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