F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 12/15/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3.2.1. TX PMA interface Parameters

Figure 60. TX PMA interface Parameters
Table 30.  TX PMA interface Parameters
Parameter Values Description
TX PMA Interface Parameters
TX PMA interface FIFO mode

Phase Compensation

Elastic

Selects the TX PMA Interface FIFO mode. Default value is Elastic.
Enable tx_pmaif_fifo_empty port On/Off Enables the port that indicates the TX PMA Interface FIFO's empty condition. Default value is Off.
Enable tx_pmaif_fifo_pfull port On/Off Enables the port that indicates the TX PMA Interface FIFO's partially full condition. Default value is Off.
TX Core Interface Parameters
Enable custom cadence generation ports and logic On/Off Enables optional custom cadence generation (CCG) logic and ports (tx_cadence, tx_cadence_fast_clk, tx_cadence_slow_clk). CCG logic can be enabled when Datapath clocking mode is set to System PLL. Default value is Off. Refer to Custom Cadence Generation Ports and Logic .
Enable tx_cadence_slow_clk_locked port On/Off

If tx_cadence_slow_clk is not directly coming from TX PLL (word clock/bond clock/user clock), but rather comes from another clock source, you must turn on the tx_cadence_slow_clk_locked port option in the parameter editor. tx_cadence_slow_clk_locked must be driven by the PLL locked output of the other PLL source used for slow clock. Default value is Off.

TX core interface FIFO mode

Phase Compensation

Elastic

Specifies the mode for the TX Core Interface FIFO. Default value is Phase Compensation. Elastic FIFO is only supported for PMA Clocking mode.
TX Tile Interface FIFO mode

Phase Compensation

Register

Specifies the mode for the TX Tile Interface FIFO. Default value is Phase Compensation.
Enable TX double width transfer

On/Off

Enables double width TX data transfer mode. In this mode, the core logic can be clocked with half rate clock. Default value is Off.
TX core interface FIFO partially full threshold 10 Specifies the partially full threshold for the TX Core Interface FIFO. Default value is 10.
TX core interface FIFO partially empty threshold 2 Specifies the partially empty threshold for the TX Core Interface FIFO. Default value is 2.
Enable tx_fifo_full port On/Off Enables the optional tx_fifo_full status output port. This signal indicates when the TX core FIFO has reached the full threshold. This signal is synchronous with tx_clkout. Default value is Off.
Enable tx_fifo_empty port On/Off Enables the optional tx_fifo_empty status output port. This signal indicates when the TX core FIFO has reached the empty threshold. This signal is synchronous with tx_clkout. Default value is Off.
Enable tx_fifo_pfull port On/Off Enables the optional tx_fifo_pfull status output port. This signal indicates when the TX core FIFO has reached the specified partially full threshold. Default value is Off.
Enable tx_fifo_pempty port On/Off Enables the optional tx_fifo_pempty status output port. This signal indicates when the TX core FIFO has reached the specified partially empty threshold. Default value is Off.
Enable tx_dll_lock port On/Off Enables the optional tx_dll_lock status output port. Monitor this signal when the core interface FIFO is in elastic mode, and then wait for the tx_dll_lock port to assert before asserting the write enable bit for the core interface FIFO. This signal indicates when the TX DLL is locked for data transfer. Default value is Off. Refer to TX and RX Parallel Data Mapping Information for Different Configurations for the write enable bit.
Enable fgt_tx_beacon port On/Off Enables or disables the fgt_tx_beacon port. Default value is Off.
TX Clock Options
Selected tx_clkout clock source

Word Clock

Bond Clock

User Clock 1

User Clock 2

Sys PLL Clock

Sys PLL Clock Div2

Specifies the tx_clkout output port source. Default value is Sys PLL Clock Div2.
Frequency of tx_clkout Output Displays the frequency of tx_clkout in MHz based on tx_clkout source selection.
Frequency of tx_clkout2 Output Displays the frequency of tx_clkout2 in MHz based on tx_clkout2 source selection and tx_clkout2 clock divide by factor.
Enable tx_clkout2 port On/Off Enables the optional tx_clkout2 output clock. Default value is Off.
Selected tx_clkout2 clock source

Word Clock

Bond Clock

User Clock 1

User Clock 2

Sys PLL Clock

Sys PLL Clock Div2

Specifies the tx_clkout2 output port source. Default value is Word Clock.
tx_clkout2 clock div by 1, 2, 4 Selects the tx_clkout2 divider setting that divides out the tx_clkout2 output port source. Default value is 1.
Selected tx_coreclkin clock network

Dedicated Clock

Global Clock

Specifies the type of clock network to use to route the clock signal to tx_coreclkin port. Dedicated clock allows a higher maximum frequency between the FPGA fabric and the F-tile interface. The number of Dedicated Clock lines are limited. Default value is Dedicated Clock.

Did you find the information on this page useful?

Characters remaining:

Feedback Message