L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
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7.2.2.2. Write DMA Internal Descriptor Controller Registers

Table 71.  Write DMA Internal Descriptor Controller RegistersThe following table describes the registers in the internal write DMA Descriptor Controller and specifies their offsets. When the DMA Descriptor Controller is externally instantiated, these registers are accessed through a user-defined BAR. The offsets must be added to the base address of the Write DMA Descriptor Controller, WrDC_SLV_ADDR. When the Write DMA Descriptor Controller is internally instantiated these registers are accessed through BAR0. The Write DMA Descriptor Controller registers start at offset 0x0100.

Address Offset

Register

Access

Description

Reset Value

0x0000

Write Status and Descriptor Base (Low

R/W

Specifies the lower 32-bits of the base address of the write status and descriptor table in the PCIe* system memory . This address must be on a 32-byte boundary.

Unknown

0x0004

Write Status and Descriptor Base (High)

R/W

Specifies the upper 32-bits of the base address of the write status and descriptor table in the PCIe* system memory.

Unknown

0x0008

Write Status and Descriptor FIFO Base (Low)

RW

Specifies the lower 32 bits of the base address of the write descriptor FIFO in Endpoint memory. The address is the Avalon-MM address of the Descriptor Controller's Write Descriptor Table Avalon-MM Slave Port as seen by the Write Data Mover Avalon-MM Master Port.

Unknown

0x000C

Write Status and Descriptor FIFO Base (High)

RW

Specifies the upper 32 bits of the base address of the write descriptor FIFO in Endpoint memory. The address is the Avalon-MM address of the Descriptor Controller's Write Descriptor Table Avalon-MM Slave Port as seen by the Write Data Mover Avalon-MM Master Port.

Unknown

0x0010

WR_DMA_LAST_PTR

RW

[31:8]: Reserved.

[7:0]: DescriptorID.

When read, returns the ID of the last descriptor requested. If no DMA request is outstanding or the DMA is in reset, returns a value 0xFF.

When written, specifies the ID of the last descriptor requested. The difference between the value read and the value written is the number of descriptors to be processed.

For example, if the value reads 4, the last descriptor requested is 4. To specify 5 more descriptors, software should write a 9 into the WR_DMA_LAST_PTR register. The DMA executes 5 more descriptors.

To have the read DMA record the Update bit of every descriptor, program this register to transfer one descriptor at a time, or set the Update bit in the WR_CONTROL register.

The descriptor ID loops back to 0 after reaching WR_TABLE_SIZE.

If you want to process more pointers than WR_TABLE_SIZE - WR_DMA_LAST_PTR, you must proceed in two steps. First, process pointers up to WR_TABLE_SIZE by writing the same value as is in WR_TABLE_SIZE, Wait for that to complete. Then, write the number of remaining descriptors to WR_DMA_LAST_PTR.

To have the write DMA record the Status Update bit of every descriptor, program this register to transfer one descriptor at a time.

[31:8]: Unknown

[7:0]:0xFF

0x0014 WR_TABLE_SIZE

RW

[31:7]: Reserved.

[6:0]: Size -1.

This register gives you the flexibility to user to specify a table size less than the default size of 128 entries. The smaller size saves memory. Program this register with the value desired - 1. .

This value specifies the last Descriptor ID.

[31:7]: Unknown

[6:0]: 0x7F

0x0018 WR_CONTROL

RW

[31:1]: Reserved.

[0]: Update.

Controls how the descriptor processing status is reported. When the Update bit is set, returns status for every descriptor processed. If not set, then only sends status back for latest entry in the WR_DMA_LAST_PTR register.

[31:1]: Unknown

[0]: 0x0

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