L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
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7.2.2.1. Read DMA Internal Descriptor Controller Registers

Figure 57. Address Offsets for Read DMA and Write DMA Internal Descriptor Controller Registers

The internal Read DMA Descriptor registers provide the following information:

  • Original location of descriptor table in host memory.
  • Required location of descriptor table in the internal Endpoint read controller FIFO memory.
  • Table size. The maximum size is 128 entries. Each entry is 32 bytes. The memory requirement is 4096 KB.
  • Additional fields to track completion of the DMA descriptors.

When you choose an internal these registers are accessed through the Read Descriptor Controller Slave.When you choose an externally instantiated Descriptor Controller these registers are accessed through BAR0. The Endpoint read controller FIFO is at offset 0x0000

The following table describes the registers in the internal Read DMA Descriptor Controller and specifies their offsets. These registers are accessed through the Read Descriptor Controller Slave. When you choose an externally instantiated DMA Descriptor Controller, these registers are accessed through a user-defined BAR. Software must add the address offsets to the base address, RdDC_SLV_ADDR of the Read DMA Descriptor Controller. When you choose an internal Descriptor Controller these registers are accessed through BAR0. The Read DMA Descriptor Controller registers start at offset 0x0000.

Table 70.  Read DMA Descriptor Controller Registers

Address Offset

Register

Access

Description

Reset Value

0x0000

Read Status and Descriptor Base (Low)

RW

Specifies the lower 32-bits of the base address of the read status and descriptor table in the PCIe* system memory. This address must be on a 32-byte boundary.

Unknown

0x0004

Read Status and Descriptor Base (High)

RW

Specifies the upper 32-bits of the base address of the read status and descriptor table in the PCIe* system memory.

Unknown

0x0008

Read Descriptor FIFO Base (Low)

RW

Specifies the lower 32 bits of the base address of the read descriptor FIFO in Endpoint memory.The address must be the Avalon-MM address of the Descriptor Controller's Read Descriptor Table Avalon-MM Slave Port as seen by the Read Data Mover Avalon-MM Master Port.

Unknown

0x000C

Read Descriptor FIFO Base (High)

RW

Specifies the upper 32 bits of the base address of the read descriptor FIFO in Endpoint Avalon-MM memory. This must be the Avalon-MM address of the descriptor controller's Read Descriptor Table Avalon-MM Slave Port as seen by the Read Data Mover Avalon-MM Master Port.

Unknown

0x0010

RD_DMA_LAST_PTR

RW

[31:8]: Reserved.

[7:0]: DescriptorID.

When read, returns the ID of the last descriptor requested. If the DMA is in reset, returns a value 0xFF.

When written, specifies the ID of the last descriptor requested. The difference between the value read and the value written is the number of descriptors to be processed.

For example, if the value reads 4, the last descriptor requested is 4. To specify 5 more descriptors, software should write a 9 into the RD_DMA_LAST_PTR register. The DMA executes 5 more descriptors.

To have the read DMA record the Update bit of every descriptor, program this register to transfer one descriptor at a time, or set the Update bit in the RD_CONTROL register.

The descriptor ID loops back to 0 after reaching RD_TABLE_SIZE.

If you want to process more pointers than RD_TABLE_SIZE - RD_DMA_LAST_PTR, you must proceed in two steps. First, process pointers up to RD_TABLE_SIZE by writing the same value as is in RD_TABLE_SIZE, Wait for that to complete. Then, write the number of remaining descriptors to RD_DMA_LAST_PTR.

[31:8]: Unknown

[7:0]:0xFF

0x0014 RD_TABLE_SIZE

RW

[31:7]: Reserved.

[6:0]: Size -1.

This register provides for a table size less than the default size of 128 entries. The smaller size saves memory. Program this register with the value desired -1.

This value specifies the last Descriptor ID.

[31:7]: Unknown

[6:0]: 0x7F

0x0018 RD_CONTROL

RW

[31:1]: Reserved.

[0]: Update.

Controls how the descriptor processing status is reported. When the Update bit is set, returns status for every descriptor processed. If not set, then sends status back for latest entry in the RD_DMA_LAST_PTR register.

The default value is 0.

[31:1]: Unknown

[0]: 0x0

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