L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

3. Interface Overview

The Intel L-/H-Tile Avalon-MM for PCI Express IP core includes many interface types to implement different functions.
These include:
  • Avalon® -MM interfaces to translate the PCIe TLPs into standard memory-mapped reads and writes
  • DMA interfaces to transfer large blocks of data
  • Standard PCIe serial interfaces to transfer data over the PCIe link or links
  • System interfaces for interrupts, clocking, reset, and test
  • Optional reconfiguration interface to dynamically change the value of configuration space registers at run-time
  • Optional status interface for debug
Unless otherwise noted, all interfaces are synchronous to the rising edge of the main system clock coreclkout_hip. You enable the interfaces using the component GUI.

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