L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

Download
ID 683667
Date 11/11/2021
Public
Document Table of Contents

7.2.1.1. Avalon-MM to PCI Express Interrupt Status Registers

These registers contain the status of various signals in the PCI Express Avalon-MM bridge logic. These registers allow MSI or legacy interrupts to be asserted when enabled.

Only Root Complexes should access these registers; however, hardware does not prevent other Avalon-MM masters from accessing them.

Table 64.  Avalon-MM to PCI Express Interrupt Status Register, 0x0060

Bit

Name

Access

Description

[31:16]

Reserved

N/A

N/A

[15:0]

AVL_IRQ_ASSERTED[15:0]

RO

Current value of the Avalon-MM interrupt (IRQ) input ports to the Avalon-MM RX master port:

  • 0—Avalon-MM IRQ is not being signaled.
  • 1—Avalon-MM IRQ is being signaled.

A PCIe* variant may have as many as 16 distinct IRQ input ports. Each AVL_IRQ_ASSERTED[] bit reflects the value on the corresponding IRQ input port.

Did you find the information on this page useful?

Characters remaining:

Feedback Message