L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
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4.4.2. Link Capabilities

Table 19.  Link Capabilities  

Parameter

Value

Description

Link port number (Root Port only)

0x01

Sets the read-only value of the port number field in the Link Capabilities register. This parameter is for Root Ports only. It should not be changed.

Slot clock configuration

On/Off

When you turn this option On, indicates that the Endpoint uses the same physical reference clock that the system provides on the connector. When Off, the IP core uses an independent clock regardless of the presence of a reference clock on the connector. This parameter sets the Slot Clock Configuration bit (bit 12) in the PCI Express Link Status register.

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