L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

7.2.1.3. Address Mapping for High-Performance Avalon-MM 32-Bit Slave Modules

Address mapping allows Avalon® -MM masters with an address bus smaller than 64 bits that are connected to the bursting Avalon® -MM slave to access the entire 64-bit PCIe* address space. The PCIe* Settings tab of the component GUI allows you to select the number and size of address mapping pages. This IP supports up to 512 address mapping pages. The minimum page size is 48 KB. The maximum page size is 4 GB.
When you enable address mapping, the slave address bus width is just large enough to fit the required address mapping pages. When address mapping is disabled, the Avalon-MM slave address bus is set to the value you specify in the GUI at configuration time. The Avalon® -MM addresses are used as-is in the resulting PCIe* TLPs.
When address mapping is enabled, bursts on the Avalon-MM slave interfaces must not cross address mapping page boundaries. This restriction means:
(address + 32 * burst count) <= (page base address + page size )

Address Mapping Table

The address mapping table is accessible through the Control and Status registers. Each entry in the address mapping table is 64 bits (8 bytes) wide and is composed of two successive registers. The even address registers holds bits [31:0]. The odd address registers holds bits [63:32].The higher order bits of the Avalon® -MM address select the address mapping window. The Avalon® -MM lower-order address bits are passed through to the PCIe TLPs unchanged and are ignored in the address mapping table.

For example, if you define16 address mapping windows of 64 KB each at configuration time and the registers at address 0x1018 and 0x101C are programmed with 0x56780000 and 0x00001234 respectively, a read or write transaction to address 0x39AB0 on the bursting Avalon® -MM slaves' interface gets transformed into a memory read or write TLP accessing PCIe address 0x0000123456789AB0.

The number of LSBs that are passed through defines the size of the page and is set at configuration time. If bits [63:32] of the resulting PCIe address are zero, TLPs with 32-bit wide addresses are created as required by the PCI Express standard.
Table 66.  Avalon-MM-to-PCI Express Address Translation Table, 0x1000–0x1FFF

Address

Name

Access

Description

0x1000

A2P_ADDR_MAP_LO0

RW

Lower bits of Avalon-MM-to-PCI Express address map entry 0.

0x1004

A2P_ADDR_MAP_HI0

RW

Upper bits of Avalon-MM-to-PCI Express address map entry 0.

0x1008

A2P_ADDR_MAP_LO1

RW

Lower bits of Avalon-MM-to-PCI Express address map entry 1.

This entry is only implemented if the number of address translation table entries is greater than 1.

0x100C

A2P_ADDR_MAP_HI1

RW

Upper bits of Avalon-MM-to-PCI Express address map entry 1.

This entry is only implemented if the number of address translation table entries is greater than 1.

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