L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

Download
ID 683667
Date 11/11/2021
Public
Document Table of Contents

6.1.1.2. Write DMA Avalon-MM Master Port

The Write Data Mover module fetches data from the Avalon-MM address space using this interface before issuing memory write requests to transfer data to PCIe* system memory.

Table 34.  DMA Write 256-Bit Avalon-MM Master Interface

Signal Name

Direction

Description

wr_dma_read_o

Output

When asserted, indicates that the Write DMA module is reading data from a memory component in the Avalon-MM address space to write to the PCIe address space.

wr_dma_address_o[63:0]

Output

Specifies the address for the data to be read from a memory component in the Avalon-MM address space .

wr_dma_read_data_i[255:0]

Input

Specifies the completion data that the Write DMA module writes to the PCIe address space.

wr_dma_burst_count_o[4:0]

Output

Specifies the burst count in 256-bit words.

wr_dma_wait_request_i

Input

When asserted, indicates that the memory is not ready to be read.

wr_dma_read_data_valid_i

Input

When asserted, indicates that wr_dma_read_data_valid_i is valid.

Figure 40. Write DMA Avalon-MM Master Reads Data from FPGA Memory

Did you find the information on this page useful?

Characters remaining:

Feedback Message