L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

6.1.6.5. Test Interface

The 256-bit test output interface is available only for x16 simulations. For x1, x2, x4, and x8 variants a 7-bit auxiliary test bus is available.

Signal

Direction

Description

test_in[66:0] Input

This is a multiplexer to select the test_out[255:0] and aux_test_out[6:0] buses. Driven from channels 8-15.

The following encodings are defined:

  • [66]: Reserved
  • [65:58]: The multiplexor selects the EMIB adaptor
  • [57:50]: The multiplexor selects configuration block
  • [49:48]: The multiplexor selects clocks
  • [47:46]: The multiplexor selects equalization
  • [45:44]: The multiplexor selects miscellaneous functionality
  • [43:42]: The multiplexor selects the PIPE adaptor
  • [41:40]: The multiplexor selects for CvP.
  • [39:31]: The multiplexor selects channels 7-1, aux_test_out[6:0]
  • [30:3]: The multiplexor selects channels 15-8, test_out[255:0]
  • [2]: Results in the inversion of LCRC bit 0.
  • [1]: Results in the inversion of ECRC bit 0
  • [0]: Turns on diag_fast_link_mode to speed up simulation.
test_out[255:0] Output

test_out[255:0] routes to channels 8-15. Includes diagnostic signals from core, adaptor, clock, configuration block, equalization control, miscellaneous, reset, and pipe_adaptor modules.

Available only for x16 variants.

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