L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

Download
ID 683667
Date 11/11/2021
Public
Document Table of Contents

3.3.2. Avalon-MM Slave Interfaces

Avalon-MM Slave Interfaces: The Avalon-MM Slave modules translate read and write transactions on their Avalon-MM interface to PCI Express MRd and MWr TLP requests. These modules return the data received in PCI Express Completion TLPs on the read data bus of their Avalon-MM interface.

Two versions of Avalon-MM Slave modules are available: the bursting Avalon-MM Slave is for high throughput transfers, and the application interface data bus width is 256-bit. The non-bursting Avalon-MM Slave is for small transfers requiring finer granularity for byte enable control. The prefix for the non-bursting Avalon-MM Slave interface is txs*. The prefix for the bursting Avalon-MM Slave interface is hptxs_*

Table 11.  Avalon-MM Slave Module Features
Avalon-MM Slave Type Data Bus Width Max Burst Size Byte Enable Granularity Maximum Outstanding Read Requests
Non-bursting 32-bit 1 cycle Byte 1
Bursting 256-bit 16 cycles DWord

32

The bursting Avalon-MM Slave adheres to the maximum payload size and maximum read request size values set by the system software after enumeration. It generates multiple PCIe TLPs for a single Avalon-MM burst transaction when required.

Table 12.  Number of TLPs generated for Each Burst Size as Function of Maximum Payload Size and Maximum Read Request Size
Burstcount Maximum Payload Size or Maximum Read Request Size
128 bytes 256 bytes 512 bytes
1 – 4 1 TLP 1 TLP 1 TLP
5 – 8 2 TLPs 1 TLP 1 TLP
9 – 12 3 TLPs 2 TLPs 1 TLP
13 – 16 4 TLPs 2 TLPs 1 TLP

Did you find the information on this page useful?

Characters remaining:

Feedback Message