L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
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6.1.3.2. Resets

The PCIe Hard IP generates the reset signal. The Avalon-MM DMA bridge has a single, active low reset input. It is a synchronized version of the reset from the PCIe IP core.
Figure 47. Clock and Reset Connections
Table 44.  Resets

Signal

Direction

Description

app_nreset_status Output This is active low reset signal. It is derived from npor or pin_perstn. You can use this signal to reset the Application.
currentspeed[1:0] Output

Indicates the current speed of the PCIe link. The following

encodings are defined:
  • 2'b00: Undefined
  • 2'b01: Gen1
  • 2'b10: Gen2
  • 2'b11: Gen3
npor

Input

The Application Layer drives this active low reset signal. npor resets the entire IP core, PCS, PMA, and PLLs. npor should be held for a minimum of 20 ns. This signal is edge, not level sensitive; consequently, a low value on this signal does not hold custom logic in reset. This signal cannot be disabled.
pin_perst

Input

Active low reset from the PCIe reset pin of the device. Resets the datapath and control registers.
ninit_done Input This is an active-low asynchronous input. A "1" on this signal indicates that the FPGA device is not yet fully configured. A "0" indicates the device has been configured and is in normal operating mode. To use the ninit_done input, instantiate the Reset Release Intel FPGA IP in your design and use its ninit_done output to drive the input of the Avalon® memory mapped IP for PCIe. For more details on how to use this input, refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an891.pdf.

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