L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

2.6. Compiling the Design Example and Programming the Device

  1. Navigate to <project_dir>/pcie_s10_hip_avmm_bridge_0_example_design/ and open pcie_example_design.qpf.
  2. On the Processing menu, select Start Compilation.
  3. After successfully compiling your design, program the targeted device with the Programmer.

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