L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

7.1.4.1. Intel Defined Vendor Specific Header

Table 55.   Intel defined Vendor Specific Header - 0xB84

Bits

Register Description

Default Value

Access

[31:20] VSEC Length. Total length of this structure in bytes. 0x5C RO

[19:16]

VSEC. User configurable VSEC revision. Not available

RO

[15:0]

VSEC ID. User configurable VSEC ID. You should change this ID to your Vendor ID. 0x1172

RO

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