L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

11.2.1.4.3. Register Address Map

Here are the base addresses when you run the as defined in link_insp_test_suite.tcl and ltssm_state_monitor.tcl.
Table 83.   PCIe* Link Inspector and LTSSM Monitor Register Addresses

Base Address

Functional Block

Access
0x00000 fPLL RW
0x10000 ATX PLL RW
0x20000 LTSSM Monitor RW
0x40000 Native PHY Channel 0 RW
0x42000 Native PHY Channel 1 RW
0x44000 Native PHY Channel 2 RW
0x46000 Native PHY Channel 3 RW
0x48000 Native PHY Channel 4 RW
0x4A000 Native PHY Channel 5 RW
0x4C000 Native PHY Channel 6 RW
0x4E000 Native PHY Channel7 RW
0x50000 Native PHY Channel 8 RW
0x52000 Native PHY Channel 9 RW
0x54000 Native PHY Channel 10 RW
0x56000 Native PHY Channel 11 RW
0x58000 Native PHY Channel 12 RW
0x5A000 Native PHY Channel 13 RW
0x5C000 Native PHY Channel 14  
0x5E000 Native PHY Channel 15 RW
0x80000 PCIe* Configuration Space RW

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