L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
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Document Table of Contents

6.1.6.2. PIPE Interface

The Intel® Stratix® 10 PIPE interface compiles with the PHY Interface for the PCI Express Architecture PCI Express 3.0 specification.
Table 48.  PIPE Interface

Signal

Direction

Description

txdata[31:0] Output

Transmit data.

txdatak[3:0] Output Transmit data control character indication.
txcompl Output Transmit compliance. This signal drives the TX compliance pattern. It forces the running disparity to negative in Compliance Mode (negative COM character).
txelecidle Output Transmit electrical idle. This signal forces the tx_out<n> outputs to electrical idle.
txdetectrx Output Transmit detect receive. This signal tells the PHY layer to start a receive detection operation or to begin loopback.
powerdown[1:0] Output Power down. This signal requests the PHY to change the power state to the specified state (P0, P0s, P1, or P2).
txmargin[2:0] Output Transmit VOD margin selection. The value for this signal is based on the value from the Link Control 2 Register.
txdeemp Output Transmit de-emphasis selection. The Intel L-/H-Tile Avalon-ST for PCI Express IP sets the value for this signal based on the indication received from the other end of the link during the Training Sequences (TS). You do not need to change this value.
txswing Output When asserted, indicates full swing for the transmitter voltage. When deasserted indicates half swing.
txsynchd[1:0] Output

For Gen3 operation, specifies the receive block type. The following encodings are defined:

  • 2'b01: Ordered Set Block
  • 2'b10: Data Block
Designs that do not support Gen3 can ground this signal.
txblkst[3:0] Output For Gen3 operation, indicates the start of a block in the transmit direction. pipe spec
txdataskip Output

For Gen3 operation. Allows the MAC to instruct the TX interface to ignore the TX data interface for one clock cycle. The following encodings are defined:

  • 1’b0: TX data is invalid
  • 1’b1: TX data is valid
rate[1:0] Output

The 2‑bit encodings have the following meanings:

  • 2’b00: Gen1 rate (2.5 Gbps)
  • 2’b01: Gen2 rate (5.0 Gbps)
  • 2’b1X: Gen3 rate (8.0 Gbps)
rxpolarity Output

Receive polarity. This signal instructs the PHY layer to invert the polarity of the 8B/10B receiver decoding block.

currentrxpreset[2:0] Output For Gen3 designs, specifies the current preset.
currentcoeff[17:0] Output

For Gen3, specifies the coefficients to be used by the transmitter. The 18 bits specify the following coefficients:

  • [5:0]: C-1
  • [11:6]: C0
  • [17:12]: C+1

rxeqeval

Output For Gen3, the PHY asserts this signal when it begins evaluation of the transmitter equalization settings. The PHY asserts Phystatus when it completes the evaluation. The PHY deasserts rxeqeval to abort evaluation.

rxeqinprogress

Output For Gen3, the PHY asserts this signal when it begins link training. The PHY latches the initial coefficients from the link partner.

invalidreq

Output For Gen3, indicates that the Link Evaluation feedback requested a TX equalization setting that is out-of-range. The PHY asserts this signal continually until the next time it asserts rxeqeval.
rxdata[31:0] Input Receive data control. Bit 0 corresponds to the lowest-order byte of rxdata, and so on. A value of 0 indicates a data byte. A value of 1 indicates a control byte. For Gen1 and Gen2 only.
rxdatak[3:0] Input Receive data control. This bus receives data on lane. Bit 0 corresponds to the lowest-order byte of rxdata, and so on. A value of 0 indicates a data byte. A value of 1 indicates a control byte. For Gen1 and Gen2 only.
phystatus Input PHY status. This signal communicates completion of several PHY requests. pipe spec
rxvalid Input Receive valid. This signal indicates symbol lock and valid data on rxdata and rxdatak.
rxstatus[2:0] Input Receive status. This signal encodes receive status, including error codes for the receive data stream and receiver detection.
rxelecidle Input Receive electrical idle. When asserted, indicates detection of an electrical idle. pipe spec
rxsynchd[3:0] Input

For Gen3 operation, specifies the receive block type. The following encodings are defined:

  • 2'b01: Ordered Set Block
  • 2'b10: Data Block
Designs that do not support Gen3 can ground this signal.
rxblkst[3:0] Input For Gen3 operation, indicates the start of a block in the receive direction.
rxdataskip Input

For Gen3 operation. Allows the PCS to instruct the RX interface to ignore the RX data interface for one clock cycle. The following encodings are defined:

  • 1’b0: RX data is invalid
  • 1’b1: RX data is valid

dirfeedback[5:0]

Input For Gen3, provides a Figure of Merit for link evaluation for H tile transceivers. The feedback applies to the following coefficients:
  • dirfeedback[5:4]: Feedback applies to C+1
  • dirfeedback[3:2]: Feedback applies to C0
  • dirfeedback[1:0]: Feedback applies to C-1

The following feedback encodings are defined:

  • 2'b00: No change
  • 2'b01: Increment
  • 2'b10: Decrement
  • 2/b11: Reserved
simu_mode_pipe Input When set to 1, the PIPE interface is in simulation mode.
sim_pipe_pclk_in Input

This clock is used for PIPE simulation only, and is derived from the refclk. It is the PIPE interface clock used for PIPE mode simulation.

sim_pipe_rate[1:0] Output

The 2-bit encodings have the following meanings:

  • 2’b00: Gen1 rate (2.5 Gbps)
  • 2’b01: Gen2 rate (5.0 Gbps)
  • 2’b10: Gen3 rate (8.0 Gbps)
sim_ltssmstate[5:0] Output

LTSSM state: The following encodings are defined:

  • 6'h00 - Detect.Quiet
  • 6'h01 - Detect.Active
  • 6'h02 - Polling.Active
  • 6'h03 - Polling.Compliance
  • 6'h04 - Polling.Configuration
  • 6'h05 - PreDetect.Quiet
  • 6'h06 - Detect.Wait
  • 6'h07 - Configuration.Linkwidth.Start
  • 6'h08 - Configuration.Linkwidth.Accept
  • 6'h09 - Configuration.Lanenum.Wait
  • 6'h0A - Configuration.Lanenum.Accept
  • 6'h0B - Configuration.Complete
  • 6'h0C - Configuration.Idle
  • 6'h0D - Recovery.RcvrLock
  • 6'h0E - Recovery.Speed
  • 6'h0F - Recovery.RcvrCfg
  • 6'h10 - Recovery.Idle
  • 6'h20 - Recovery.Equalization Phase 0
  • 6'h21 - Recovery.Equalization Phase 1
  • 6'h22 - Recovery.Equalization Phase 2
  • 6'h23 - Recovery.Equalization Phase 3
  • 6'h11 - L0
  • 6'h12 - L0s
  • 6'h13 - L123.SendEIdle
  • 6'h14 - L1.Idle
  • 6'h15 - L2.Idle
  • 6'h16 - L2.TransmitWake
  • 6'h17 - Disabled.Entry
  • 6'h18 - Disabled.Idle
  • 6'h19 - Disabled
  • 6'h1A - Loopback.Entry
  • 6'h1B - Loopback.Active
  • 6'h1C - Loopback.Exit
  • 6'h1D - Loopback.Exit.Timeout
  • 6'h1E - HotReset.Entry
  • 6'h1F - Hot.Reset

sim_pipe_mask_tx_pll_lock

Input

Should be active during rate change. This signal Is used to mask the PLL lock signals. This interface is used only for PIPE simulations.

In serial simulations, The Endpoint PHY drives this signal. For PIPE simulations, in the Intel testbench, The PIPE BFM drives this signal.

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