L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

7.1.7. Correctable Internal Error Status Register

Table 61.  Correctable Internal Error Status Register - 0xBBCThe Correctable Internal Error Status register reports the status of the internally checked errors that are correctable. When these specific errors are enabled by the Correctable Internal Error Mask register, they are forwarded as Correctable Internal Errors. This register is for debug only. Only use this register to observe behavior, not to drive logic custom logic.

Bits

Register Description

Reset Value

Access

[31:12]

Reserved.

0

RO

[11] Correctable ECC error status for Config RAM. 0 RW1CS
[10] Correctable ECC error status for Retry Buffer. 0 RW1CS
[9] Correctable ECC error status for Retry Start of TLP RAM. 0 RW1CS
[8] Reserved. 0 RO
[7] Reserved. 0 RO
[6] Internal Error reported by FPGA. 0 RW1CS

[5]

Reserved

0

RO

[4]

PHY Gen3 SKP Error occurred. Gen3 data pattern contains SKP pattern (8'b10101010) is misinterpreted as a SKP OS and causing erroneous block realignment in the PHY.

0

RW1CS

[3] Correctable ECC error status for RX Buffer Header RAM #2. 0

RW1CS

[2] Correctable ECC error status for RX Buffer Header RAM #1. 0

RW1CS

[1]

Correctable ECC error status for RX Buffer Data RAM #2.

0

RW1CS

[0]

Correctable ECC error status for RX Buffer Data RAM #1.

0

RW1CS

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