L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

Download
ID 683667
Date 11/11/2021
Public
Document Table of Contents

3.5. System Interfaces

TX and RX Serial Data

This differential, serial interface is the physical link between a Root Port and an Endpoint. The PCIe IP Core supports 1, 2, 4, 8, or 16 lanes. Gen1 at 2.5 GT/s, Gen2 at 5 GT/s and Gen3 at 8 GT/s are supported. Each lane includes a TX and RX differential pair. Data is striped across all available lanes.

PIPE

This is a parallel interface between the PCIe IP Core and PHY. The PIPE data bus is 32 bits. Each lane includes four control/data bits and other signals. It carries the TLP data before it is serialized. It is available for simulation only and provides more visibility for debugging.

Interrupts

The Stratix® 10 Avalon-MM DMA Bridge can generate legacy interrupts when the Interrupt Disable bit, bit[10] of the Configuration Space Command register is set to 1'b0.

The Avalon-MM Bridge does not generate MSIs in response to a triggering event. However, the Application can cause MSI TLPs, which are single DWORD memory writes, to be created by one of the Avalon-MM slave interfaces.

To trigger an MSI, the Application performs a write to the address shown in the msi_intfc[63:0] bits, using the data shown in the msi_intfc[79:64] bits with the lower bits replaced with the particular MSI number.

The Application can also implement MSI-X TLPs, which are single DWORD memory writes. The MSI-X Capability structure points to an MSI-X table structure and MSI-X pending bit array (PBA) structure which are stored in system memory. This scheme is different than the MSI capability structure, which contains all the control and status information for the interrupts.

Hard IP Reconfiguration

This optional Avalon® -MM interface allows you to dynamically update the value of read-only Configuration Space registers at run-time. It is available when Enable dynamic reconfiguration of PCIe read-only registers is enabled in the component GUI.

If the PCIe Link Inspector is enabled, accesses via the Hard IP Reconfiguration interface are not supported. The Link Inspector exclusively uses the Hard IP Reconfiguration interface, and there is no arbitration between the Link Inspector and the Hard IP Reconfiguration interface that is exported to the top level of the IP.

Hard IP Status

This optional interface includes the following signals that are useful for debugging

  • Link status signals
  • Interrupt status signals
  • TX and RX parity error signals
  • Correctable and uncorrectable error signals

Did you find the information on this page useful?

Characters remaining:

Feedback Message