L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
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6.1.4.1. MSI Interrupts for Endpoints

The Stratix® 10 PCIe Avalon-MM Bridge with DMA does not generate an MSI to signal events. However, the Application can cause an MSI to be sent by the non-bursting Avalon-MM TX slave by performing a memory write to the non-bursting Avalon-MM TX slave.

After the host receives an MSI it can service the interrupt based on the application-defined interrupt service routine. This mechanism allows host software to avoid continuous polling of the status table done bits. This interface provides the required information for users to form the MSI/MSI-X via the TXS interface.

Table 45.  MSI Interrupt

Signal

Direction

Description

msi_intfc[81:0]

Output

This bus provides the following MSI address, data, and enabled signals:

  • msi_intfc_o[81]: Master enable
  • msi_intfc_o[80]: MSI enable
  • msi_intfc_o[79:64]: MSI data
  • msi_intfc_o[63:0]: MSI address

msix_intfc_o[15:0]

Output

Provides for system software control of MSI-X as defined in Section 6.8.2.3 Message Control for MSI-X in the PCI Local Bus Specification, Rev. 3.0. The following fields are defined:

  • msix_intfc_o[15]: Enable
  • msix_intfc_o[14]: Mask
  • msix_intfc_o[13:11]: Reserved
  • msix_intfc_o[10:0]: Table size
msi_control_o[15:0]

Output

Provides system software control of the MSI messages as defined in Section 6.8.1.3 Message Control for MSI in the PCI Local Bus Specification, Rev. 3.0. The following fields are defined:

  • msi_control_o[15:9]: Reserved
  • msi_control_o[8]: Per-Vector Masking Capable
  • msi_control_o[7]: 64-Bit Address Capable
  • msi_control_o[6:4]: Multiple Message Enable
  • msi_control_o[3:1]: MSI Message Capable
  • msi_control_o[0]: MSI Enable
intx_req_i

Input

Legacy interrupt request.

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