8. Programming Model for the DMA Descriptor Controller
The Avalon-MM DMA Bridge module includes an optional DMA Descriptor Controller. When you enable this Descriptor Controller, you must follow a predefined programming model.This programming model includes the following steps:
- Prepare the descriptor table in PCIe* system memory as shown in the following figure.
Figure 58. Sample Descriptor Table
- Program the descriptor table, providing the source and destination addresses and size for all descriptors.
- For intermediate status updates on the individual descriptors, also program the RD_CONTROL or WR_CONTROL Update bits. Refer to the sections Read DMA Internal Descriptor Controller Registers and Write DMA Internal Descriptor Controller Registers for the descriptions of these bits.
- Tell the DMA Descriptor Controller to instruct the Read Data Mover to copy the table to its own internal FIFO.
- Wait for the MSI interrupt signaling the completion of the last descriptor before reprogramming the descriptor table with additional descriptors. You cannot update the descriptor table until the completion of the last descriptor that was programmed.
Here is an example for the following configuration:
- An Endpoint including the Avalon® -MM Bridge with the DMA IP core
- The internal DMA Descriptor Controller
- The non-bursting Avalon® -MM slave
Host software can program the Avalon® -MM DMA Bridge’s BAR0 non-bursting Avalon-MM master to write to the DMA Descriptor Controller’s internal registers. This programming provides the information necessary for the DMA Descriptor Controller to generate DMA instructions to the PCIe Read and Write Data Movers. The DMA Descriptor Controller transmits DMA status to the host via the Avalon-MM DMA Bridge’s non-bursting Avalon-MM slave interface. The DMA Descriptor Controller's non-bursting Avalon-MM master and slave interfaces are internal and cannot be used for other purposes.
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